SystemVerilog for Hardware Description: RTL Design and Verification (Record no. 50867)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 01416 a2200169 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20250721121714.0 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9789811544071 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.951 TAR |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Taraate, Vaibbhav |
| 245 ## - TITLE STATEMENT | |
| Title | SystemVerilog for Hardware Description: RTL Design and Verification |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Name of publisher, distributor, etc | Springer |
| Date of publication, distribution, etc | 2021 |
| Place of publication, distribution, etc | Pune |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 252 |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | System Verilog |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | RTL Design |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Book |
| Source of classification or shelving scheme | Dewey Decimal Classification |
No items available.
