000			01416 a2200169 4500
005			20250721121714.0
020			_a9789811544071
082			_a621.951 TAR
100			_aTaraate, Vaibbhav
245			_aSystemVerilog for Hardware Description: RTL Design and Verification
260			_bSpringer _c2021 _aPune
300			_a252
520			_aThis book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC.
650			_aSystem Verilog
650			_aRTL Design
942			_cBK _2ddc
999			_c50867 _d50867