000			01612 a2200181 4500
005			20251113084638.0
020			_a9788197374043
082			_a004.22 KHA
100			_aKhadgi, Mitesh
245			_aIntroduction to Universial Verification Methodology
250			_a1
260			_bShine Book Publishing _c2024 _aChhattisgarh
300			_a248
520			_aUVM is a methodology based on SystemVerilog language and is not a language on its own. It is a standardized methodology that defines several best practices in verification to enable efficiency in terms of reuse and is also currently part of IEEE 1800.2 working group. Universal Verification Methodology (UVM) verification is a set of standards, tools, and APIs for creating a universal way of verifying designs. This API/ methodology is meant for building functional testbenches for SoCs. UVM being constructed in SystemVerilog is supported by simulators from all vendors, enabling you to be more productive during the digital design process. End users can consider it a toolbox with tools and instructions for important verification tasks. This book is for people who want to get an overview of UVM. Generally, the books which are published on UVM are ten times more expensive than this book. In this book, you can find sufficient number of examples to understand any topic in UVM. After reading this book, you would be able to implement, and figure out different ways to verify any design under consideration using Universal Verification Methodology (UVM).
650			_aMethodology
650			_aComputer programming techniques
942			_cBK _2ddc
999			_c51934 _d51934