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Writing Testbenches Using System Verilog / by Janick Bergeron.

By: Material type: TextTextPublication details: New Delhi: Springer (India) Private Limited, c2006Description: xxvi, 412 p. : ill. ; 25 cmISBN:
  • 9788184892697
Subject(s): DDC classification:
  • 621.392 BER 22
LOC classification:
  • TK7885.7 .B48 2006
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Holdings
Item type Current library Collection Call number Status Date due Barcode Item holds
Book Book Alliance College of Engineering and Design Electronics and Communication Engineering 621.392 BER (Browse shelf(Opens below)) Available E08893
Book Book Alliance College of Engineering and Design Electronics and Communication Engineering 621.392 BER (Browse shelf(Opens below)) Available E08894
Book Book Alliance College of Engineering and Design SC & ST Book Bank - Mezzanine Floor Electronics and Communication Engineering 621.392 BER (Browse shelf(Opens below)) Available E08895
Book Book Alliance College of Engineering and Design Electronics and Communication Engineering 621.392 BER (Browse shelf(Opens below)) Claim 2016-17 E08896
Book Book Alliance College of Engineering and Design Electronics and Communication Engineering 621.392 BER (Browse shelf(Opens below)) Available E08897
Book Book Alliance College of Engineering and Design Electronics and Communication Engineering 621.392 BER (Browse shelf(Opens below)) Available E08898
Reference Book Reference Book Alliance College of Engineering and Design Electronics and Communication Engineering 621.392 BER (Browse shelf(Opens below)) Not for loan E08471
Book Book Alliance College of Engineering and Design Electronics and Communication Engineering 621.392 BER (Browse shelf(Opens below)) Available E08472
Book Book Alliance College of Engineering and Design Electronics and Communication Engineering 621.392 BER (Browse shelf(Opens below)) Available E08473
Book Book Alliance College of Engineering and Design Electronics and Communication Engineering 621.392 BER (Browse shelf(Opens below)) Available E08474
Total holds: 0

This book presents the same concepts as the second edition of Writing testbenches, functional verification of HDL models, but uses System Verilog as the sole implementation vehicle. The languages used in the second edition are still available.

Includes bibliographical references and index.

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