Guide to RISC Processors: For Programmers and Engineers

By:

Dandamudi, Sivarama P

Publication details: New Delhi: Springer (India) Private Limited, 2005Description: 387ISBN:

9788181286635

Subject(s):

DDC classification:

004.3 DAN

Summary: Recently, there has been a trend toward processors based on the RISC (Reduced Instruction Set Computer) design. This is an accessible and all-encompassing compendium on RISC processors, introducing five of them: MIPS, SPARC, PowerPC, ARM, and Intel's 64-bit Itanium. Initial chapters explain differences between the CISC and RISC designs, and the core RISC design principles are clearly discussed. Later chapters provide instruction on MIPS assembly language programming, so that readers can readily learn the concepts and principles introduced earlier. Professionals, programmers, and students in computer architecture and programming courses will find the guide an essential resource

List(s) this item appears in: New Arrivals for the Month of September - 2023

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Holdings
Item type	Current library	Collection	Call number	Status	Date due	Barcode	Item holds
Book	Alliance College of Engineering and Design	CSE & IT	004.3 DAN (Browse shelf(Opens below))	Available		E12257

Total holds: 0

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Recently, there has been a trend toward processors based on the RISC (Reduced Instruction Set Computer) design. This is an accessible and all-encompassing compendium on RISC processors, introducing five of them: MIPS, SPARC, PowerPC, ARM, and Intel's 64-bit Itanium. Initial chapters explain differences between the CISC and RISC designs, and the core RISC design principles are clearly discussed. Later chapters provide instruction on MIPS assembly language programming, so that readers can readily learn the concepts and principles introduced earlier. Professionals, programmers, and students in computer architecture and programming courses will find the guide an essential resource

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